FIG. 23 is a circuit diagram showing a linearizer according to a first conventional example (see, for example, Patent Document 1). The linearizer according to the first conventional example as shown in FIG. 23 includes: a signal path in which an input terminal 1 into which a radio frequency band signal (RF signal) is inputted, an input side bias blocking capacitor 4, a diode 8, an output side bias blocking capacitor 5, and an output terminal 2 from which the radio frequency band signal is outputted are connected in series in the stated order; a bias circuit in which a first resistor 7 is connected between a signal path formed between the input side bias blocking capacitor 4 and the diode 8 and a bias terminal 3; an RF short-circuit capacitor 6 whose one end is connected with a bias circuit between the bias terminal 3 and the first resistor 7 and whose other end is grounded; a bias short-circuit inductor 11 whose one end is connected with a signal path formed between the diode 8 and the output side bias blocking capacitor 5 and whose other end is grounded; and a series circuit composed of a second resistor 9 and a first capacitor 10 which are connected in parallel with the diode 8.
This linearizer is an example of an analog predistortion linearizer. The linearizer is connected in series with an amplifier in the preceding or subsequent stage thereof. Then, the distortion of the amplifier having a characteristic in which a gain is increased with an increase in input power and a phase is delayed therewith is compensated by the linearizer. According to the linearizer, when a bias voltage, a value of the resistor 9, and a value of the capacitor 10 are changed, an input power-gain characteristic (AM-AM characteristic) and an input power-phase characteristic (AM-PM characteristic) can be adjusted.
FIG. 24 is a circuit diagram showing a linearizer according to a second conventional example (see, for example, Patent Document 2). In FIG. 24, the same reference numerals are applied to the same portions as those shown in FIG. 23 and the description thereof is omitted here. In the linearizer according to the second conventional example as shown in FIG. 24, two diodes 8 and 12 are used in parallel with opposite polarities to each other with respect to the RF signal. A direct current bias is connected in series with each diode in the forward polarity direction. Resistors 21 and 22 are provided in parallel with the diodes 8 and 12. The bias is applied through each of resistors 19 and 20.
When the above-mentioned linearizer is connected in series with an amplifier in the preceding or subsequent stage thereof, the distortion of the amplifier having a characteristic in which a gain is increased with an increase in input power and a phase is delayed therewith is compensated by the linearizer. When values of the resistors 21 and 22 are changed, the input power-gain characteristic (AM-AM characteristic) and the input power-phase characteristic (AM-PM characteristic) can be finely adjusted.
FIG. 25 is a circuit diagram showing a linearizer according to a third conventional example (see, for example, Patent Document 3). In FIG. 25, the same reference numerals are applied to the same portions as those shown in FIG. 23 and the description thereof is omitted here. In the linearizer according to the third conventional example as shown in FIG. 25, two diodes 23 and 24 form a diode pair provided in parallel with opposite polarities to each other and one terminal of each thereof is grounded with respect to the RF signal. Resistors 31 and 32 are used for a voltage divider.
FIG. 26 is a circuit diagram showing a harmonic mixer according to a fourth conventional example (see, for example, Patent Document 4). In the harmonic mixer according to the fourth conventional example as shown in FIG. 26, a low-pass lifter 28 and a DC cut 27 are provided on a path between an IF input terminal 30 and an IF input terminal 29. Two diodes 23 and 24 connected in parallel with opposite polarities to each other and a line 25 having a λ/4 wavelength relative to a local signal are provided between a connecting point between the low-pass lifter 28 and the DC cut 27 and ground. Reference numeral 26 denotes a line having the λ/4 wavelength relative to the local signal and 31 denotes a local signal input terminal.
Patent Document 1: JP 2002-76784 A (FIG. 1)
Patent Document 2: Japanese Utility Model Application Laid-open No. Sho 61-68517 (FIG. 1)
Patent Document 3: Japanese Utility Model Application Laid-open No. Hei 05-023612 (FIG. 1)
Patent Document 4: JP 09-130236 A (FIG. 5)